DOI 10.17586/0021-3454- 2017-60-10-967-972
UDC 004.27
AN APPROACH TO DESIGN OF FPGA-BASED SYSTEMS FOR STREAM DATA PROCESSING WITH CAPABILITY OF COMBINED DEBUGGING
LMT Ltd., Saint Petersburg, 199034, Russian federation; Engineer
Read the full article
Abstract. Debugging of computational FPGA-based systems oriented on stream data processing is considered. An effective debugging procedure for a systems models and prototypes it is necessary to use unified input and output data. The proposed approach is based on a specific procedure of design of FPGA projects and their test environments. This provides compatibility of data formats, generation the necessary input/output test data, and debugging in various representations of designed system. A set of components to be reused when creating a debug infrastructure is presented. The described approach is oriented for implementation in the framework of existing design flows and CAD tools for FPGA-based projects.
Keywords: debugging, verification, design, FPGA, FPGA based system, chip based system, CAD
References:
References:
- Meyer-Baese U. Digital Signal Processing with Field Programmable Gate Arrays, Springer, 2001.
- Sinha R., Roop P., Basu S. Correct-by-Construction Approaches for SoC Design, Springer, 2013.
- Mitra S., Seshia S.A., Nicolici N. 47th ACM/IEEE Design Automation Conference (DAC), 13–18 June 2010. DOI: 10.1145/1837274.1837280
- Goeders J., Wilton S.J.E. 24th International Conference on Field Programmable Logic and Applications (FPL), 2–4 Sept. 2014, DOI: 10.1109/FPL.2014.6927498
- Stollon N., Leatherman R. DesignCon East, 2005.
- Adir A., Copty S., Landa S., Nahir A., Shurek G., Ziv A., Meissner C., Schumann J. Design, Automation & Test in Europe Conference & Exhibition (DATE), 14–18 March 2011. DOI: 10.1109/DATE.2011.5763252
- Teich J. Proceedings of the IEEE, 2012, vol. 100, pp.1411–1430.
- Platunov A., Kluchev A., Penskoi A. 6th International Congress on Ultra Modern Telecommunications and Control Systems and Workshops (ICUMT), 2014, pp. 157–164.
- Xilinx System Generator for DSP, Xilinx, Inc. System Generator for DSP Getting Started Guide UG639 (v11.4). December 2, 2009, www.xilinx.com.
- Wagner I., Bertacco V. IEEE International Conference on Computer Design, 12–15 Oct. 2008. DOI: 10.1109/ICCD.2008.4751878
- Antonov A.A., Bykovskiy S.V., Kustarev P.V. Journal of Instrument Engineering, 2014, no. 4(57), рр. 53–57.
- Leens F. FPGA verification tools need an upgrade, Exostiv Labs, 2015.
- Certus ASIC Prototyping Debug Solution, Tektronix, Inc., 2012.
- Abramovici M., Bradley P., Dwarakanath K., Levin P., Memmi G., Miller D. Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, 24–28 July, 2006. DOI: 10.1145/1146909.1146916
- Da Silva F., McLaurin T., Waayers T. The Core Test Wrapper Handbook. Rationale and Application of IEEE Std. 1500, Springer Science+Business Media, LLC, 2006.
