Flexible tuning of neural network processor performance by parametrizing the architecture

The problem of designing hardware accelerators for edge artificial intelligence systems is considered, taking into account the limitations on the resources used. A modular parameterizable architecture of the neural network processor is been developed, which allows flexibly adjusting the characteristics of the accelerator, including the size of computing elements and the size of the internal buffer memory, to the requirements of the target system. The effectiveness of the obtained results is confirmed by modeling a neural network accelerator at the level of register transfers using the parameters of the convolutional layer of the YOLOv5s neural network. The dependence of the crystal area on the architecture parameters using the programmable logic unit (Field Programmable Gate Array, FPGA) of the ZYNQ-7000 system on a chip is investigated. It has been shown that increasing the size of the systolic array increases productivity, but the effect of the increase decreases with large values. Scaling the systolic array also increases the number of logic gates and single-bit registers of the FPGA. Increasing the amount of internal memory significantly affects the consumption of FPGA block memory elements, but does not significantly affect overall performance. The experimental results confirmed the advantage of the proposed approach in terms of adaptability and flexibility of customization for various application scenarios. Promising areas of application are systems that require high performance with limited resources. The results obtained can serve as a basis for the development of new generations of neural network processors with the ability to scale performance and taking into account resource constraints.

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