ISSN 0021-3454 (print version)
ISSN 2500-0381 (online version)

vol 67 / May, 2024

DOI 10.17586/0021-3454-2017-60-6-513-518

UDC 681.32


A. V. Grekov
Perm Military Institute of National Guard Troops of the Russian Federation, Department of Software Computer Technology and Automated Systems; Associate Professor

S. F. Tyurin
Perm National Research Polytechnic University, Department of Automation and Telemechanics; Professor

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Abstract. Logical element of programmable logic integrated circuits of FPGA (field-programmable gate array) type is called in foreign sources LUT (Look Up Table), i.e. it is essentially a truth table of a logic function. This implementation is based on the perfect disjunctive normal forms (PDNF) representation of the logic functions that require significant hardware costs, as opposed to the implementation in the disjunctive normal form (DNF), used with the 70-ies of XX century in the programmable logic array (PLA). At the same time, much of the logic functions implemented by a number k of conjunctions is much smaller than the total number of sets of n binary variables. However, for programming the PLA requires special programmers, whereas the configuration LUT is loaded into random access memory (RAM or SRAM). A DNF-LUT is proposed to implement a system of logical functions in DNF which significantly reduces the hardware cost of implementing the logic of programmable logic integrated circuits with no deterioration of the performance. Complexity of the proposed technical solutions and the results of functional simulation are analyzed.
Keywords: logical element, PLD of FPGA type, Look Up Table, disjunctive normal form, transistor

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