Abstract. An original method is proposed for designing architecture of hardware computational units on FPGA, ASIC, and hybrid SoC platforms, and corresponding CAD prototype framework is developed. The method is based on hierarchy of “Language IP” (LIP) cores — specialized hardware description languages with embedded translators that implement target hardware unit generation based on input user specification. In terms of configurability, LIP cores lay between the traditional cores, which are configured by the standard means of hardware description language itself, and full standalone translators with their own specific languages and autonomous compiler infrastructure. In comparison with designing based on clear industrial HDLs or using standalone translators from high-level languages, the proposed method facilitates selective fixation of useful microarchitectural decisions with support of implementation of custom user functionality and, at the same time, does not require specific engineering qualification in the field of formal syntaxes of programming languages. The method and CAD prototype are demonstrated by the example of LIP implementing the pipeline mechanism, and a training CPU core with DLX architecture built on the base of the LIP. Advantages and shortcomings of the proposed method are evaluated, and directions of future research are formulated.

Keywords: embedded systems, system-on-chip, SoC, microarchitecture, CAD, RTL, HLS, domainspecific language

References:

1. Hartenstein R., Kaiserslautern T.U., Karlsruhe K.I.T. SE Curricula are Unqualified to Cope with the Data Avalanche, 2017, рp. 1–20, http://hartenstein.de/publications/CS.pdf.
2. Platunov A.E. Journal of Instrument Engineering, 2014, no. 4(57), рр. 49–52. (in Russ.)
3. Mishra P., Dutt N. Processor Description Languages, Morgan Kaufmann Publishers Inc., 2008.
4. Nane R. et al. IEEE Trans. Comput. Des. Integr. Circuits Syst., 2015, no. 10(35), рр. 1591–1604.
5. Skalicky S. Int. Conf. ReConFigurable Comput., FPGAs, 2015, рp. 0–5.
6. Klyuchev A.O., Antonov A.A. Programmnye produkty i sistemy, 2016, no. 4, рр. 78–84. (in Russ.)
7. Greaves D.J. ACM/IEEE Int. Conf. Form. Methods Model, Codesign, 2015, рp. 108–117.