ISSN 0021-3454 (print version)
ISSN 2500-0381 (online version)
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5
Issue
vol 60 / MAY, 2017
Article
UDC 681.327

TRANSACTION-LEVEL REAL-TIME CONSTRAINTS MONITOR FOR SYSTEM ON CHIP

A. A. Antonov
ITMO University; Student


S. . Bykovsky
Saint Petersburg National Research University of Information Technologies, Mechanics and Optics; “LMT”, Ltd; postgraduate; engineer,


P. V. Kustarev
ITMO University; Associate Professor


Abstract. A method of the formal description of internal timing restrictions for computing systems at transaction level is proposed. The method is focused on reduction of hardware complexity of embedded monitoring and diagnostics tools. Based on the proposed approach, the timing restrictions hardware monitor for systems on chip (SoC) with bus-topology is designed, and results of its experimental implementation are presented.
Keywords: SoC, real-time constraints, constraints monitor, RTL, TLM, SVA, PSL, LTL, CTL