ISSN 0021-3454 (print version)
ISSN 2500-0381 (online version)
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12
Issue
vol 59 / DECEMBER, 2016
Article
UDC 004.384:004.272:004.414.2

CHECKING UP ISOMORPHIC INCLUSIONS OF R-EXPRESSIONS IN THE CONSTRUCTION OF A SET OF SECTIONS FOR PARALLEL LOGIC CONTROL ALGORITHMS

E. I. Vatutin
Kursk State Technical University, Department of Computer Technique;


I. V. Zotov
Kursk State Technical University, Department of Computer Technique; Professor


V. S. Titov
Southwest State University, Department of Computer Science, Kursk; Professor, Head of Department


Abstract. In the paper a hardware-level algorithm is proposed for checking up isomorphism (r-isomorphism) of R-expression trees (sections of parallel algorithm) based upon a number of R-expression tree features. A description for the corresponding hardware (accelerator) is presented to check up isomorphism of R-expressions in linear time
Keywords: logic multicontroller, synthesis, parallel logic control algorithm, separation, optimization, oriented trees.