TRANSACTION-LEVEL REAL-TIME CONSTRAINTS MONITOR FOR SYSTEM ON CHIP
ITMO University; Student
S. V. Bykovsky
ITMO University, Saint Petersburg, 197101, Russian Federation; Associate Professor
P. V. Kustarev
ITMO University; Associate Professor
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Abstract. A method of the formal description of internal timing restrictions for computing systems at transaction level is proposed. The method is focused on reduction of hardware complexity of embedded monitoring and diagnostics tools. Based on the proposed approach, the timing restrictions hardware monitor for systems on chip (SoC) with bus-topology is designed, and results of its experimental implementation are presented.
Keywords:
SoC, real-time constraints, constraints monitor, RTL, TLM, SVA, PSL, LTL, CTL
