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vol 64 / May, 2021
Article

DOI 10.17586/0021-3454-2016-59-7-558-562

UDC 621.396.6

USE OF PARETO DIAGRAM FOR ENSURING QUALITY OF INTEGRATED CIRCUIT FUNCTIONING

A. V. Averianov
Mozhaysky Military-Space Academy, Department of Information and Computing Systems and Networks;


T. I. Belaya
A. F. Mozhaysky Military Space Academy, Department of Data Processing Systems and Networks;


O. E. Molchanov
A. F. Mozhaysky Military Space Academy, Department of Data Processing Systems and Networks;


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Abstract. An approach to the problem of ensuring quality of semiconductor devices and integrated circuits (IMS) functioning is proposed. The approach is based on application of Pareto chart demonstrating dependence of an IMS failure on the type of its defect. The main types of defects causing the major part of IMS failures are defined.
Keywords: Pareto analysis, Pareto diagram, operation quality, failure, reliability, integrated circuit

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