ISSN 0021-3454 (print version)
ISSN 2500-0381 (online version)
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Issue
vol 65 / June, 2022
Article

DOI 10.17586/0021-3454-2022-65-4-231-246

UDC 004.052.32+681.518.5

WEIGHTED CODES WITH SUMMATION IN THE RING OF RESIDUES BY AN ARBITRARY MODULUS FOR THE SYNTHESIS OF DIGITAL COMPUTING DEVICES

D. V. Ephanov
PSTU; Department of Automation and Telemechanics on the Railways


V. P. Artyom
Russian University of Transport, Department of Automation, Remote Control, and Communications on Railway Transport;


Abstract. In the synthesis of self-checking and fault-tolerant digital computing systems, binary redundant codes are often used. Their use makes it possible to reduce structural redundancy in order to endow devices with the property of self-checking or fault tolerance. Results of the study of a wide class of codes with summation are presented, in the construction of which preselected sequences of weight coefficients and the summation procedure in the ring of residues by a preliminarily fixed modulus are used. Codes with three sequences of weight coefficients are considered: 1) natural numbers; 2) natural series except for powers of 2; 3) alternating sequences of increasing powers of the number 2. Characteristics of error detection by codes by multiplicities and types (monotonic, symmetric and asymmetric) are established. Conditions for constructing noise-immune codes, as well as methods for modifying codes to endow them with the property of noise immunity, are given. Results of experiments with control combinational circuits on the use of the described codes for error detection at their outputs are presented. The features of the use of modular weighted codes with summation in the synthesis of digital devices are discussed
Keywords: self-checking and fault-tolerant devices, codes with summation, error detection in information vectors, summation in the ring of residues modulo, weight coefficients of digits

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