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vol 67 / November, 2024
Article

DOI 10.17586/0021-3454-2022-65-5-307-322

UDC 004.052.32+681.518.5

TERNARY MODULAR CODES WITH SUMMATION FOR THE SYNTHESIS OF DIGITAL SELF-TESTING DEVICES

D. V. Ephanov
PSTU; Department of Automation and Telemechanics on the Railways


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Abstract. Ternary summation codes with simple construction rules, suitable for the digital self-checking circuits synthesis operating in ternary logic and able of detecting any non-compositional errors in information vectors (when the number of characters of each type is preserved), are considered. Rules for constructing the ternary sum codes, similar in its properties to the Berger binary code, are given. Two modifications of the ternary sum code are described – sum codes in the residues modulo μ=3 and μ=9 ring. Several characteristics of error detection by the codes are described. It is shown that the proportion of errors of multiplicity d, undetectable by binary summation codes, of the total number of errors of the given multiplicity, is a constant value independent of the information vector length.
Keywords: fault-tolerant and self-testing digital devices and systems, noise-resistant and noise-proof coding, ternary codes with summation, error detection in information vectors, undetectable error

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