The intensive development of the theory of computer-aided design is taken place today is associated with requirements to designers to increase their efficiency of work with simultaneous improvement of quality and reliability of projects. To satisfy the requirements, the denial of the classical principles of automated design formulated more than half a century ago may be necessary. Therefore, the task of development of computer-aided design technologies meeting all qualifying standards is quite challenging. The main approach to the problem is to improve the level of automation in design processes. It is appropriate to use Knowledge Engineering technique, which calls for development of modern or modification of existing methods of knowledge representation. A new method of infological modeling for representation of knowledge in a uniform manner is proposed. The theory of categories is presumed to be used as a mathematical apparatus. The presented infological models specify the general structure of verbal symbolic constructions at the three levels of abstraction. The developed method can be used at the stage of integration and coordination of knowledge within the general cycle of the automated design.

Development and usage of ontologies is an important part of modern text analysis application. When huge amount of text is analyzed, the lookup time in ontology becomes critical bottleneck. An approach to creation of search prefix tree of wordforms’ parts called x-gram is proposed. Division of the wordform into 3- and 4-gramms as well as phonetic and morphological syllable for Russian language is used. Every x-gram is represented by numerical index that allows its storage in the plain array. Resulting arrays are very sparse, so approach uses compactification to “insert” one array into another. When looking for a word, it is split into x-grams, the index for every x-gram is computed, consequent lookup is performed in constructed arrays, where each array corresponds to a single level of prefix tree. The developed program demonstrates the advantage of 36—50 % over Google dense hash-map in seek time and 12 % over Google sparse hash-map in memory consumption for set of Russian wordforms extracted from wellknown grammatical dictionary and Russian National Corpus. This approach is well suited for dictionary search in rarely changing wordform sets, such as ontology based on Russian Wiktionary.

A method is proposed for sandbox implementation for potentially malicious applications including those which received malicious characteristics after infection. The method is based on redirection of access requests based on patented technical solution. The sandbox implementation method produces minimal impact on end machine productivity and is easily administrated; an example of practical interest application is presented. The described technical solution is tested in a commercial information security system.

The possibility of reserved service of copies of requests critical to delay is studied for duplex computer system of cluster architecture with sequential execution of queries (first at the cluster nodes lower, then at the upper level). An analytical model is presented for estimation of probability of timely service of requests for the case when the total waiting time for upper- and low-level nodes does not exceed a preset limiting value, and no errors and crashes occur during the stay of the queries requests critical to delay both levels. Effectiveness of reserved service is evaluated for requests critical to summarized waiting delay in the upper- and low-level nodes. Areas of effective application of the proposed approach to reserved service copies of requests are described, and optimal multiplicity of the requests copying is determined.

A method is proposed for estimating the capacity of internal buffer memory of the router for networks with priority-based traffic control. The traffic with arbitrary distribution of lengths of packets of different classes is considered. Priority queueing management is based on a discipline with mixed priorities. A formula is derived for the capacity of the router buffer memory required to store packets of each class for a given probability of buffer overflow. The account of the dependence of required buffer memory capacity on the type of distribution of packet lengths is shown to be necessary to ensure quality of service for short-term bursts in traffic speed and to prevent packet loss.

The problems of discrete system simulation and parametrization are discussed. The intensity of traffic is shown to be one of the main parameters to be used in network modeling. A method is proposed for determination of probability distribution law for the time intervals between the packets in various computer networks. Based on the obtained results, it is concluded that split of the interval between the packets into several shorter segments allows to reduce the deviation of the model from the original, and hence to ensure the simulation to give adequate results.

The organization of memory in modern multi-core multiprocessor systems causes the problem of false split of CPU cash string addressed in the paper. The false CPUs cache lines split makes tasks scheduled to be run in parallel by several cores, are executed sequentially. The problem is difficult to detect, and its presence can cause a sharp degradation of the system performance. Programming patterns which give rise to the problem are identified. The templates execution time is measured in the presence of false splitting and after applying the methods proposed in the work to solve the problem. The effect of the number of threads running in parallel on the speed-up of programming templates execution and the efficiency of utilization of the system computing resources are analyzed. It is shown experimentally that the false split significantly affects temporal characteristics of multi-threaded applications. Several methods to eliminate the difficulties are proposed.

Debugging of computational FPGA-based systems oriented on stream data processing is considered. An effective debugging procedure for a systems models and prototypes it is necessary to use unified input and output data. The proposed approach is based on a specific procedure of design of FPGA projects and their test environments. This provides compatibility of data formats, generation the necessary input/output test data, and debugging in various representations of designed system. A set of components to be reused when creating a debug infrastructure is presented. The described approach is oriented for implementation in the framework of existing design flows and CAD tools for FPGA-based projects.

The problems of using corrective codes in traditional digital angle converters based on the absolute reference method are analyzed. It is shown that the problems are caused by significant redundancy in the code tracks number proportional to the block length of the code used, as well by the increased technological complexity of manufacturing the scale code mask. The above features usually lead to an increase in device size and to difficulties in eliminating the ambiguity of reading. A possibility of application of methods of error-correcting coding in digital angle converters with single-track recursive code scales is demonstrated. A generalized methodology is proposed and an algorithm for the reading elements positioning on the scale is developed for arbitrary parameters of block length, the minimum code distance, and the field of coefficients of the generator polynomial for the correction code. Examples of use of the described methodology for the minimum code distance of 3 and 5 are presented. It is shown that practical employment of error-proof coding methods based on cyclic codes always leads to correct location of the sensing elements regardless of the structure of the recursive code scale. For truncated cyclic codes, a sufficient condition for correctness is given.

An original method is proposed for designing architecture of hardware computational units on FPGA, ASIC, and hybrid SoC platforms, and corresponding CAD prototype framework is developed. The method is based on hierarchy of “Language IP” (LIP) cores — specialized hardware description languages with embedded translators that implement target hardware unit generation based on input user specification. In terms of configurability, LIP cores lay between the traditional cores, which are configured by the standard means of hardware description language itself, and full standalone translators with their own specific languages and autonomous compiler infrastructure. In comparison with designing based on clear industrial HDLs or using standalone translators from high-level languages, the proposed method facilitates selective fixation of useful microarchitectural decisions with support of implementation of custom user functionality and, at the same time, does not require specific engineering qualification in the field of formal syntaxes of programming languages. The method and CAD prototype are demonstrated by the example of LIP implementing the pipeline mechanism, and a training CPU core with DLX architecture built on the base of the LIP. Advantages and shortcomings of the proposed method are evaluated, and directions of future research are formulated.

An approach to evaluation of parameters of flying vehicle orientation using analysis of registering camera video-stream is discussed. The proposed methodology allows to obtain the data independently of course, pitch, and roll sensors of the flying vehicle and, thus, enables an emergency positioning feature in case of a fault. Video stream analysis employed in the method for frame-by-frame tracking of key peculiarities of the images (e.g., contrast details) is based on modifications of the standard Shi—Tomasi—Kanade algorithm. In particular, the developed modification of the algorithm allows affine distortions of features, as well as local changes in their brightness. An algorithm is proposed for estimating the flying vehicle spatial orientation using the found set of features via the equivalent shift of the recording camera. The obtained values can be used for analysis both in real time and in post-processing mode.

The problems of computational platforms design for cyber-physical systems are analyzed. The main progressive methods of system / architectural design of specialized computer facilities and automation are presented, which can form the basis of a complex methodology for designing new generation of cyberphysical systems. The definitions of the concepts "computing platform", "high-level design" of embedded systems and systems on a chip are given. The methodology and technology "Platform-oriented design", "Actor design", ESL-design, high-level synthesis of systems on a chip, "Contract-oriented design" in the context of creating embedded and cyber-physical systems are considered. The principles of the HLD methodology created and developed at the Department of Computation Technologies of ITMO University are presented.